Many modern integrated circuits are fabricated according to complementary-metal-oxide-semiconductor (CMOS) technology, where both p-channel and n-channel MOS transistors are formed in the same semiconductor chip. CMOS technology provides good performance together with much reduced power consumption, as compared with other technologies such as bipolar and n-channel MOS. As is well known, however, CMOS structures have present a parasitic thyristor, or SCR, formed by alternating p-type and n-type structures. If the CMOS integrated circuit is exposed to a voltage which is above the firing voltage of the parasitic SCR, a latchup condition can occur. Once the structure is in latchup, destructive amounts of current can be drawn through the SCR, often damaging the integrated circuit.
Many techniques for reducing the tendency of latchup for a given integrated circuit have been utilized. One such technique is the provision of a substrate bias which is more negative than the ground, or common, potential provided to the integrated circuit. Of course, such negative substrate bias is also useful for other reasons, such as improving the performance of the integrated circuit by raising the threshold voltage of enhancement-mode n-channel MOS transistors. However, the presence of the negative substrate bias can ensure that the base-emitter junction of one of the parasitic bipolar transistors in the parasitic SCR does not become forward-biased for reasonable excursions of voltages applied to the integrated circuit. Without the forward-biased condition at the base-emitter junction of the parasitic bipolar transistor, latchup by way of the parasitic SCR cannot occur.
Such negative substrate bias can be provided by way of a voltage applied to the integrated circuit chip from an external power supply; the necessity for such an external power supply is not favored by many integrated circuit users, due to the increase in the system cost required to provide such a power supply. Accordingly, a preferred way of providing substrate bias at a voltage more negative than the chip ground potential is by way of a charge pump. Examples of charge pump circuits for providing substrate bias are described in U.S. Pat. No. 4,585,954, issued Apr. 29, 1986, U.S. Pat. No. 4,628,215, issued Dec. 9, 1986, and in U.S. Pat. No. 4,631,421, issued Dec. 23, 1986, all assigned to Texas Instruments Incorporated and incorporated herein by this reference. Whether the substrate bias is applied from external to the chip or generated on-chip, if the substrate bias is lost for some reason, the integrated circuit can become vulnerable to the latchup condition.
It is therefore an object of this invention to provide a circuit which can detect the loss of proper substrate bias.
It is a further object of this invention to provide such a circuit on-chip with a VLSI integrated circuit.
It is a further object of this invention to provide such a circuit where the level at which substrate bias is detected does not strongly depend upon transistor sizes or channel width/length ratios.
It is a further object of this invention to provide an integrated circuit which has on-chip circuitry to disable power supply voltages from portions of the chip responsive to loss of proper substrate bias.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.